You have msr xxx,reg (move to special register) and mrs reg,xxx (move from special register). Here "xxx" is the special register (such as PRIMASK) and the few special registers that there are all have nice distinct names.
So, what about PRIMASK? How many priority levels are supported? As it turns out this is a single bit (in a 32 bit register)
I use the following macros:
#define INT_enable() asm volatile ( "cpsie i" : : : "memory") #define INT_disable() asm volatile ( "cpsid i" : : : "memory")Some code makes statements like "this sets the I-bit in the CPSR in order to disable interrupts." As far as I know the Cortex-M doesn't have a CPSR, so this statement may well be true on other architectures, but it is misleading here. The Cortex-M has PRIMASK as an independent register all its own.
Sometimes documentation just doesn't explain things you wish it did. I understand why this happens. If the documentation writers understand what they are writing about (and we hope that they do), it is easy for them to forget what someone new to all of this does and doesn't know. In truth, dealing with this very issue is what separates the men from the boys when it comes to writing good documentation. In the meanwhile, we have to resort to experiments many times to clarify issues that good documentation ought to clarify.
What else might be masked? NMI obviously not, just by name. Hard fault? I doubt it. svcall? Maybe.
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