Orange Pi 4 (Rockchip 3399) Introduction to the GIC 500

Here is what I know about the GIC in general. The GIC in essence is a matrix for routing interrupts to different cores. The GIC can be configured so that one core handles interrupts from one device and another core handles interrupts from another device. An operating system could be arranged so that one "master" core handled all interrupts and other cores were devoted to running user processes. Alternately one core could be devoted to network processing and it alone could receive network device interrupts. The GIC is versatile and allows designs of all sorts to be conceived. Note that designs like I just described run contrary to general SMP. However having a big/little core discrimination also runs counter to SMP (and linux ignores those core distinctions assigning cores at random). But I am waxing philosophical and need to get back to GIC500 details.

• ARM developer: the GIC family
• GIC / processor compatibility table
• GIC "getting started" document
• GIC-500 online reference manual
• GIC-500 online refman - introduction

PDF documents entitled "GIC Architecture specification v3 and v4" are available. What seems to be the latest one is 921 pages and dated 2021.

Notes on the GIC-500

It has a single base address. There seem to be 3 main components:

• GICD registers - distributor
• GICR registers - redistributor
• GITS registers - ITS (Interrupt translation service)