There is no clear winner. Verilog seems most commonly used in the USA and VHDL elsewhere. This seems odd given that VHDL was designed in the USA by the DOD> People say you will end up using both. Vivado will accept either, along with "system verilog".
I was amused by the following advice. If you are in the USA, learn Verilog. If you get a defense related job, use the time waiting for your security clearance to learn VHDL.
VHDL is stricter, with a more rigorous and detailed type system. It is also less like C programming, which may be good for a habitual C programmer like myself -- it will remind me I am doing logic design not writing programs.
I am coming at this from an entirely different angle, wanting exclusively (and immediately) to be able to synthesis designs and run them on an FPGA. I understand the value of simulation and "testbench" code prior to synthesis.
Enough axe grinding. Here are some links that spell out (in part at least) which constructs are allowed in synthesis and which are not.
Here is my partial list of things that are not allowed in synthesis:Tom's Computer Info / [email protected]