July 9, 2022

FPGA - Verilog and VHDL

Which should you learn?

There is no clear winner. Verilog seems most commonly used in the USA and VHDL elsewhere. This seems odd given that VHDL was designed in the USA by the DOD> People say you will end up using both. Vivado will accept either, along with "system verilog".

I was amused by the following advice. If you are in the USA, learn Verilog. If you get a defense related job, use the time waiting for your security clearance to learn VHDL.

VHDL is stricter, with a more rigorous and detailed type system. It is also less like C programming, which may be good for a habitual C programmer like myself -- it will remind me I am doing logic design not writing programs.

Synthesis versus Simulation

I find it endlessly annoying that virtually all of the Verilog books and resources fail to make it clear that there are two ways to use the language. Synthesis refers to "compiling" the design into a form that can be loaded into an FPGA. There are many Verilog constructs that pertain only to simulation and which cannot be used in synthesis. Why don't books have a table or appendix that spells this out? Many books are written with simulation only in mind (since students in a classroom setting may deal only with simulation and have no access to FPGA hardware). Such books start to treat Verilog like yet another programming language and lure the student into thinking this way, which is at best misleading. I suppose the idea is that they will learn about synthesis on the job after they graduate.

I am coming at this from an entirely different angle, wanting exclusively (and immediately) to be able to synthesis designs and run them on an FPGA. I understand the value of simulation and "testbench" code prior to synthesis.

Enough axe grinding. Here are some links that spell out (in part at least) which constructs are allowed in synthesis and which are not.

Here is my partial list of things that are not allowed in synthesis:
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Tom's Computer Info / [email protected]