(Note: this generates a simple FPGA design using Vivado and ends up with it running on the Zybo).
I have Vivado installed on my linux system, and the aim here is to see if I can build and run a trivial FPGA example. I don't want to do anything yet with the Arm side (the "PS") of the Zynq, but just use JTAG to download and run an FPGA design.
I am going to power the board using 5 volts from the barrel jack. This requires moving a jumper near the barrel jack to connect the center pin (marked VV5VO) to "Wall".
Another jumper near the VGA connector can be installed in 3 ways. Right now it is on "SD", I move it to the other side to "JTAG"
One other blue jumper is present on the board on JP1 near the USB OTG connector and is marked "HOST". I leave this jumper in place. Whether it is present or absent would only matter if I was using one of the two USB-OTG connectors next to this jumper.
The USB connection I want to use to download FPGA configuration is next to the power switch. I connect a micro USB cable to this.
The following page is extremely thorough and useful as far as exploring the jumpers and physical features of the board:
Warning. Don't have too many wall warts plugged in! I just made the mistake of plugging in the 12 volt wart that I had been using for my Zedboard, which just happened to be nearby and plugged into AC. I may even put clear labels on the ends of my wall wart plugs. No damage seemed to occur, but this certainly is not good.
With the proper 5 volt supply, I see in my linux logs:
May 14 08:23:37 trona kernel: usb 3-1: new high-speed USB device number 3 using xhci_hcd May 14 08:23:37 trona kernel: usb 3-1: New USB device found, idVendor=0403, idProduct=6010, bcdDevice= 7.00 May 14 08:23:37 trona kernel: usb 3-1: New USB device strings: Mfr=1, Product=2, SerialNumber=3 May 14 08:23:37 trona kernel: usb 3-1: Product: Digilent Adept USB Device May 14 08:23:37 trona kernel: usb 3-1: Manufacturer: Digilent May 14 08:23:37 trona kernel: ftdi_sio 3-1:1.0: FTDI USB Serial Device converter detected May 14 08:23:37 trona kernel: usb 3-1: Detected FT2232H May 14 08:23:37 trona kernel: usb 3-1: FTDI USB Serial Device converter now attached to ttyUSB0 May 14 08:23:37 trona kernel: ftdi_sio 3-1:1.1: FTDI USB Serial Device converter detected May 14 08:23:37 trona kernel: usb 3-1: Detected FT2232H May 14 08:23:37 trona kernel: usb 3-1: FTDI USB Serial Device converter now attached to ttyUSB1 May 14 08:23:38 trona kernel: ftdi_sio ttyUSB0: FTDI USB Serial Device converter now disconnected from ttyUSB0 May 14 08:23:38 trona kernel: ftdi_sio 3-1:1.0: device disconnectedIt is odd that ttyUSB0 disconnected. Also I see no mention of any udev related activity, which I might expect from the "cable drivers" I installed with Vivado, but we will press on and see how things go.
The board has a red power LED lit.
Now we are all set up and back to the "Project Manager". I use "Add sources", design sources, create file, name the file "top.v", and Finish. Now I am asked to "define module", which lets me name ports. I make two ports. I do not select "Bus" or enter MSB, LSB
button as input led as output
Now in the "Sources" box, I expand "Design Sources", then double click "top.v" when it is exposed. This gives me an editor over to the right in "Project Summary" and shows me some boilerplate code that has been generated for me. I add one line to this as follows:
assign led = button;I click "save file" (which is an Icon that looks like an ancient floppy disk) at the top of the editor window.
Now for constraints. Again I use "Add sources", but select constraints, then create file. I name the file "top.xdc" (you have to "know" that constraint files are xdc files apparently). Then finish. Now in the Sources box I can expand "Constraints" and see top.xdc within constrs_1. I double click this and it opens in an editor window to the right.
I can squint at my Zybo board and see pin names on the silscreen as follows:
button 0 is R18 LED 0 is M14The following is a "master constraint file" for the Zybo. They instruct you to copy this, uncomment the relevant lines, and change the signal names to match what you are using. I find the following:
#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L20N_T3_34 Sch=BTN0 #set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L23P_T3_35 Sch=LED0I change this to the following and paste it in for top.xdc. Then click the save Icon at the top.
set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { button }]; set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { led }];Now, with these two files in place I ought to be able to continue.
At the left side of the GUI in what they call "Flow Navigator" there is a scrollbar. I can scroll down and see things that were hidden before. Or I can just drag the entire window down to make it bigger and see everything. This exposes:
Generate bitstream Open Hardware ManagerI take these in order. First "generate bitstream". Again I hear lots of disk activity and wait patiently (sort of). Indeed, after a ridiculous time, a popup tells me that the bitstream has been successfully generated. I click OK to dismiss this.
Now for Hardware Manager. No new GUI opens up, but at the top of the screen it tells me that no hardware target is open. I click on the blue text "open target" and select autoconnect. This seems to work. I am now offered "program device", and a "Hardware" box now shows a hierarchy of hardware (arm_dap_0 and xc7z010_1). I click on the blue text "program device" and get a dialog asking me to select a bitstream. It has already found "top.bit", so I click the program button. After a progress bar, a green LED on the Zynq is lit (labeled "DONE").
And it works!! I press Button 0 and I see LED 0 light up accordingly. Very nice.
Also it is particularly nice to find that accidently connecting the 12 volt supply did no damage.
It is also nice to confirm that my cable driver setup in fact is working, despite no messages
showing up in my log files related to udev and USB setup.
Tom's Computer Info / [email protected]