February 23, 2023

EBAZ4205 - A Vivado "cheat sheet" for simple projects

By simple, I mean projects that don't require anything at all to do with Block Designs and the IP integrator. I hear you already. Is this even possible? It depends. If all you want to do is write verilog and all the signals you need are in the constraint file, it is.

An example would be a project for the Zybo or Zedboard where you have a clock fed into an FPGA pin (and hence in the constraint file), or when you just want to used buttons as inputs and turn on LEDs.

Starting vivado

To start vivado, I type "vivado" on the command line. This starts vivado 2019.1 -- I don't see any compelling reason to upgrade, though a Xilinx popup has suggested it many times.

New Project

I use File -- Project -- New which gives me a new project "wizard". I give the project a name (ez_blink). I let it use the usual /home/tom/vivado as the location. I call it an RTL project. I skip both "add sources" and "add constraints" for now. (You can use the "+" button in the "Sources" tab to add these later.

Select the board (not the part)

The next wizard dialog takes some care. It gives me a menu with a long list of parts, but I want to switch to "Boards" at the top of this dialog. Then I pull down the "vendor" menu and scan for "miner", when I select that, the Ebaz is the only choice (this is because I added "board files" many months ago.). Now I finish the new project dialog and I am in Vivado proper.

Editing

An important side note. I often edit external to vivado using vim. I also configure vivado to use vim (via Tools -- Settings). Sadly this runs vim in an xterm with a while background and it is more or less unreadable with the vim colorscheme. Type :colo desert for a much more reasonable setup. Or type :syntax off.

Add the constraint file

Use the "+" button at the top of the Sources tab.

I keep my master constraint files at: 

/u1/Projects/FPGA/Ebaz/Ebaz_Master.xdc
/u1/Projects/FPGA/Zedboard/Zedboard-Master.xdc
/u1/Projects/Zybo/ZYBO_Master.xdc

Be sure to copy it, not just let vivado link to it. If vivado is stubborn and just makes a link (as it always does), there is a menu entry when you right click on the file that says "copy file into project" that will fix things for you.

Then you will want to edit it and uncomment those signals you intend to use (my master file for the Ebaz has all signals commented out).

This file is also on my Github page:

It ends up at a location like this (which you will need to know to edit it). 
/u1/home/tom/vivado/ez_blink/ez_blink.srcs/constrs_1/imports/Ebaz/Ebaz_Master.xdc
I always use vim external to vivado the edit files. You can double click on files, and you can make vim the editor vivado launches in such cases. Currently vim uses some horrible color scheme when you do so.

Take note of the "official" names for the actual pins you intend to use in the constraint file. These will need to match signal names in your verilog code.

Add a verilog file

RTL is "register transfer language" and in my case is verilog.

Adding a verilog file is much the same game as adding the constraint file. You can add the file and follow the dialog for ports and it will set up a "prototype" file with declarations for the ports, or if you are a veteran you will know what to do and and skip all that and write your own verilog.

Here is an example: 

module blinker(
    input button,
    output led1,
    output led2
    );

    assign led1 = button;
    assign led2 = ~button;
endmodule
Note that "button", "led1", and "led2" will need to match pin names in the constraint file.

The end game

Run synthesis
Run implementation (skip "open implemented design"
Generate bitstream
Each of these takes considerable time. Keep an eye on the upper right corner of Vivado where messages appear telling you what it is doing (along with a spinning circle arrow to indicate that it is busy and things are in progress).

Run the design

If you have the proper "cable" (in the Xilinx lingo, a cable is some kind of cable and gadget that connects to the chip FPGA, you can have Vivado load and run the generated bitstream.

When generate bitstream finishes, it typically offers to just open hardware manager for you.

For the Ebaz there are some non-obvious steps. First you need to have the pico USB gadget plugged in on the JTAG port and the xvcd-pico server running in some window and listening on port 2542 (which is what it normally does). Then in the vivado hardware manager, click on localhost(0) to get a menu and select "Add Xilinx Virtual Cable". Enter (select) localhost in the popup this yields. It will default to port 2542 and should show you a JTAG hierarchy, with xc7z010_1 already selected. Click on "program device" near the top of the screen and it should bring up a dialog to select the bitstream file (with the one and only bitstream already selected). Confirm this and you get a progress bar and Success!.

I test flew all this with the Ebaz on 2/25/2023. My verilog simply set the red_led and green_led to 0 and 1. This worked fine. Using the built in vim scheme and issuing the command to fix colors avoided chasing crazy directory paths for the constraint and verilog files. This probably saved time and fuss.

For the Zybo -- go to Hardware manager, it should offer blue text "open target". Do this and select autoconnect. You should next be offered "program device" along with a hardware hierarchy (you probably want xc7z010_1). A dialog will allow you to select a bitstream (and there will probably be just one). Click the "program" button. It should load and run your bitstream. Keep an eye on the Green LED (DONE) next to the Zynq.

You should be running your design.

Feedback? Questions? Drop me a line!

Tom's Computer Info / [email protected]